Engineering for Mission Success
Formed to provide contract engineering service in 2013 for analog, digital, software, and reliability engineering. Expertise in worst case circuit analysis for analog and digital designs for aerospace client customers. Company and partner FPGA/ASIC verification engineering and FPGA design engineers. Sub-tier NASA/JPL contractor through client Bastion Technologies Corp. L3-SSG Corporation contractor for Worst Case Circuit Analysis and Failure Modes, Effects, and Criticality Analysis (Mil-Std-1629A part level analysis)
Engineering Staffing Pursuit and Research and Development
Recruiting electrical engineers, worst case analysts, reliability analysts, FPGA design engineers, and RTL functional verification engineers for contract engineering tasks, turnkey designs, and SBIR/STTR business development.
What We Do
Worst Case Analysis, Reliability Analysis
Signal flow graph transfer function derivations. Analytical model correlation to Pspice models. EVA, RSS, Monte Carlo analyses. Analytical models developed in Mathcad, Mathematica, and MATLAB. Board level design engineering and signal integrity analysis.
FMECA, Piece part, functional, and interface. Predictions, Part Stress Analysis, Fault tree analysis, Single Event Effects, and PRA.
Spaceflight FPGA designs in Microsemi and Xilinx FPGA platforms. High speed SERDES designs. Communication protocols, RS-422, I2C, SPI, MIL-STD-1553, USB. Application specific requirements, such as DSP. Xilinx, ISE, Vivado, Microsemi Libero, and Altera/Intel Quartus. VHDL, Verilog RTL designs.
Functional Verification Engineering
Verification engineering test plans and execution for successfully bringing up FPGA designs in the lab or ASICs: Code coverage, assertions, self-checking test benches, automatic stimulus, and functional coverage. System Verilog and UVM test benches.