Our Services

Worst Case Circuit Analysis, Reliability Engineering,

FPGA Design, RTL Functional Verification,

Services

What We Do

 

Worst Case Analysis, Reliability Analysis

 

Signal flow graph transfer function derivations.  Analytical model correlation to Pspice models.  EVA, RSS, Monte Carlo analyses.  Analytical models developed in Mathcad, Mathematica, and MATLAB.  Board level design engineering and signal integrity analysis.

FMECA, Piece part, functional, and interface.  Predictions, Part Stress Analysis, Fault tree analysis, Single Event Effects, and PRA.

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FPGA Design
Engineering

 

Spaceflight FPGA designs in Microsemi and Xilinx FPGA platforms.  High speed SERDES designs.  Communication protocols, RS-422, I2C, SPI, MIL-STD-1553, USB.  Application specific requirements, such as DSP.  Xilinx, ISE, Vivado, Microsemi Libero, and Altera/Intel Quartus.  VHDL, Verilog RTL designs.

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Functional Verification Engineering

 

Verification engineering test plans and execution for successfully bringing up FPGA designs in the lab or ASICs:  Code coverage, assertions, self-checking test benches, automatic stimulus, and functional coverage.  System Verilog and UVM test benches.

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our services

Meeting your requirements

and project execution.

We tailor our services to your unique project requirements. Our focus is on supporting our customers through worst case circuit analysis, FPGA design engineering, RTL functional verification, and turnkey design engineering service. We partner with prime contractors and consultant partners on their projects and internal SBIR and STTR pursuits. We work with you to produce concurrent engineering service that meets and exceeds  the statement of work and project objectives. Assist in interface to your customers,  as applicable for project success.

Worst Case Analysis, Reliability Analysis:

Develop worst case analyses that correlate to your hardware design and incorporate beginning of life, temperature, and aging for analog and digital worst case timing. Reliability engineering analyses: Prediction, FMECA, Part Stress, Fault Tree, and PRA especially for space and defense applications.

Pencil

Worst Case Analysis of Mechanism Control Electronics for Space Based Imaging

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Design portfolios and proposals available upon request.

Part level FMECA analyses Space Based Imaging Electronics

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Design portfolios and proposals available upon request.

Spacecraft Bus and Instrument Worst Case Analyses, Fault Tree Analysis, Part Stress Analysis, Single Event Effects Analysis, and Interface FMECAs

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Design portfolios and proposals available upon request.

Analytical and Spice modeling of electrical systems for ensuring accuracy and performance

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Design portfolios and proposals available upon request.

Architectural Trade Studies, Reliability Predictions, Fault Tree Analysis, and PRA per NASA guidelines

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Design portfolios and proposals available upon request.

FPGA Design Engineering:

FPGA design requirements development: functional and performance specifications, register map, memory map, and pin out. RTL design in VHDL and Verilog. VHDL and Verilog self-checking test Benches, and code coverage with System Verilog.

FPGA

Expertise in Communication Protocols and Interfaces (SERDES, I2C, SPI, ARM based protocols)

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Design portfolios and proposals available upon request.

Signal Processing (DSP), IIR, FIR, CIC Filter Design

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Design portfolios and proposals available upon request.

Server Class System on a Chip (SOC) Design and Verification

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Design portfolios and proposals available upon request.

Space Flight FPGA and Board Design Integration, Sensor electronics, Signal Integrity, Stack-up Design, and DFM

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Design portfolios and proposals available upon request.

FPGA design and verification for wireless communication and instrumentation

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Design portfolios and proposals available upon request.

Functional Verification Engineering:

Verification engineering test plans and executions for successfully bringing up FPGA designs in the lab or ASICs: Code coverage, assertions, Self-checking test benches, automatic stimulus, and functional coverage. System Verilog and UVM test benches.

FPGA 2

Design Verification of FPGAs & ASICs using Specman E, System Verilog (UVM/OVM/VMM)

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Design portfolios and proposals available upon request.

System Level Test Benches, RTL and Gate Level Simulation and Debug for Portable Electronics

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Design portfolios and proposals available upon request.

Design and Develop Subsystem Block Level Test Benches for cellular communication products, Agent/Driver, Test/Sequence, Gate-Level simulations. Develop Functional Verification Cover Point/Cover Groups.

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Design portfolios and proposals available upon request.

Design UVM Test Benches for AMD ARM based Processors connected through ARM fabric. Design of BFMs and stimulus for I2C, SPI, and ARM protocols (AXI, AHB, APB, CHI).

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Design portfolios and proposals available upon request.

FPGA Verification of Aerospace Products and ASIC Functional Verification for Hard Drive Controller SOC designs

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Design portfolios and proposals available upon request.

The Experience You Need

Subject Matter Expertise in Worst Case Analysis, FPGA design, and Functional Verification Engineering.

Customer Satisfaction Focused

Deliver high quality service to your schedule and project requirements.

Initial Consultation and Quotation Support

Highly motivated to propose services that support your project objectives.

HEADQUARTERS

Erie, Colorado

 

 

CALL US

 720-519-0587

 

 

EMAIL US

info@rightparadigmconsulting.com